Design of a C-Band CMOS class AB power amplifier for an ultra low supply voltage of 1.9 V

Abstract

Present day power amplifier (PA) design struggles with the fact that applicable supply voltages are continuously shrinking for short channel MOS transistors, which makes reaching high output power values increasingly difficult. This work develops a Class AB PA with an optimized load impedance for maximum output power with the help of a systematic load- pull analysis. It will display necessary trade offs for optimum output power and small signal gain. The presented PA, realized in CMOS, shows a measured output power of 19.8 dBm at 5.8 GHz for a supply voltage of 1.9 V. The drain efficiency at the 1 dB compression point reaches 28.1 %, the highest report up to today for this output power level.