Design of a 1.8V 10bit 300MSPS CMOS digital-to-analog converter with a novel deglitching circuit and inverse thermometer decoder

Abstract

In this paper, a 1.8 V 10 bit 300 MSPS CMOS digital-to-analog converter (DAC) is described. The architecture of the D/A converter is based on a current steering 8+2 segmented type, which reduces non-linearity errors and other secondary effects. In order to achieve a high performance D/A converter, a novel current cell with a low spurious deglitching circuit and a novel row/column 4 to 15 inverse thermometer decoder are proposed. To verify the performance, the device is integrated with 0.25 /spl mu/m CMOS 1-poly 5-metal technology. The effective chip area is 1.56 mm/sup 2/ and power consumption is about 84 mW at 2.5 V power supply. The simulation and experimental results show that the glitch energy is 0.9 pV/spl times/sec at fs=100 MHz, 15 pV/spl times/sec at fs=300 MHz in worst case, respectively. Furthermore, both INL and DNL are within /spl plusmn/1.0 LSB, and the SFDR is about 59 dB when the sampling frequency is 300 MHz and output frequency is 3 MHz.