Design of 8 and 16 Bit LFSR with Maximum Length Feedback Polynomial & Its pipelined Structure Using Verilog HDL

Abstract

This paper is mainly concerned with the design of random sequences using Linear Feedback Shift Register (LFSR). This pseudo sequences is mainly used for various communication purposes. The other application such as banking, cryptographic, encoder & decoder. For hardware prototype FPGA is used because of its flexibility to reconfigure design many times. LFSR is a shift register whose output random state depends upon feedback polynomial. But by using pipelined architecture we can reduce the timing of random pattern generated at output by reducing the critical path. It can count maximum 2n-1 states and produce pseudo-random number at the output. Finally, comparing the simple and pipelined architecture of 8 & 16-bit LFSR.