Design of 1.8V LVDS Transmitter in GF 22nm For Associative Memory

Abstract

This paper presents the design of Low Voltage Differential Signaling (LVDS) transmitter for Associative Memory (AM). AM is used in High Energy Physics (HEP) experiments like Large Hadron Collider (LHC). AM can store up to one billion patterns. The proposed design works for IO supply of 1.8V and core supply of 1V with an output voltage swing of 350mV over 1.2V offset voltage. This design is implemented in 22nm FDSOI technology to work across process corners and is simulated using cadence virtuoso tool. This design is met the required data rate of 1Gbps for AM application with power consumption of 12.34mW.