Design of 16-Bit Vedic Multiplier Using Modified Logic Gates and BEC Technique

Abstract

AbstractHigher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications. Thus, for the design of an efficient arithmetic unit, the key functioning elements are multipliers, adders, and the basic logic gates for which the performance parameters which decide the complete performance of the arithmetic unit are area, power dissipation, and speed. Research has been going through the past few decades to design efficient VLSI arithmetic circuits by using logic optimization and circuit optimization techniques to further reduce area, power, and delay. The multiplier design which is initially developed for area optimizations is an array multiplier in which the main disadvantage is the worst-case delay. To overcome this disadvantage, many methodologies came into existence in which Vedic methodology has acquired prominence because of fast computations. It has been found that Vedic multiplier adopting Urdhva Tiryagbhyam is one of the most effective multipliers with minimum delay for multiplication of all types of numbers, either large or small. Though the speed of this multiplier is high, area occupancy is more. Thus, Binary to Excess-one Converter (BEC) technique is employed in this multiplier to reduce area. To further improve the performance, a 16 × 16 Vedic multiplier employing BEC adders and modified logic gates is developed and coded in Verilog HDL and further synthesized using Vivado 2017.2. Synthesis results disclose that the 16-bit Vedic multiplier using BEC technique employing Modified AND gate and Modified OR gate architecture accomplishes power savings of 0.13% compared to a Vedic multiplier using BEC technique. KeywordsVedic multiplierUrdhva tiryagbhyamBEC techniqueModified logic gates