Abstract
This paper presents a 16-bit 100MS/s SAR ADC with 1V power supply for biomedical implant systems developed with low power technique i.e., DTMOS logic. It consists of a R-2R DAC, low-power comparator, a digital SAR logic with low-leakage. The designed comparator is a differential architecture that has used to have an excellent, common-mode noise rejection. Comparator was created for proper operation to remain in saturation and could be used with differential amplifier. The comparator is the chief block of power consumption, so we focused mainly much of ability we make to design this module. The ADC is designed using Cadence virtuoso with CMOS 45nm technology. For SFDR, SNR, ENOB and power consumption, the converter utilizes 63.97dB, 51.06 dB, 15.15 and 528.8uw.
Highlights
The role of ADC is vital in the bi-signal processing; for noiseless signal processing, data conversion is essential
Article History: Received: 10 November 2020; Revised: 12 January 2021; Accepted: 27 January 2021; Published online: 05 April 2021 Abstract: This paper presents a 16-bit 100MS/s SAR ADC with 1V power supply for biomedical implant systems developed with low power technique i.e., DTMOS logic
The comparator is the chief block of power consumption, so we focused mainly much of ability we make to design this module
Summary
The role of ADC is vital in the bi-signal processing; for noiseless signal processing, data conversion is essential. Data converters speed is not much concern These devices are implanted on the human body since they should be operated with ultra-low power and powered by harvested energy [59-60]. Several improved and hybrid systems includingsuch as Flash pipeline, SAR pipeline, SARflash is developed and discussed [1].to enhance processing speed and power consumption optimization These ADCs have reduced the group of components, and that is not better to adjust power consumption beyond a certain limit.SAR ADC has becoming a bigger subject to study for its excellent power efficiency. It will be used for applications of medium resolution, high speed and low power and small section. The observations and analysis of the simulation are given in the Section IV and Section V
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