Design Methodology for Rapid Development of SoC ICs Based on an Innovative System Architecture with Emphasis to Timing Closure and Power Consumption Optimization

Abstract

Complex System on Chip (SoC) ICs require a high development effort and extensive testing in order to meet performance and power consumption specifications. Those requirements are usually achieved through laborious and iterative procedures which engage synthesis, timing, power analysis and back-end tools. Traditional design methodologies deal with the above issues from a synthesis or technology point of view, trying to optimize the propagation delay of primitive cells, simplifying the logic and disabling the clocks when possible. This presentation describes how a design methodology can be combined with an innovative architecture, called COMBA, for system on chip ICs in order to help the designer to achieve timing closure and meet performance and power consumption requirements in short time. This methodology is supported by tools that produce the gate level description of the system using pre-optimized building blocks for the COMBA architecture, leading to minimum development and testing time while preserving the performance and power requirements.