Design Methodology for High-Level Synthesis

Abstract

In the previous chapters we have defined synthesis, presented target architectures and design-quality measures, discussed description languages and design representations and presented algorithms for partitioning, scheduling and allocation for synthesis on higher-than-logic abstraction levels. In this chapter we will combine those ideas into a design methodology for synthesis on system and chip levels. System-level synthesis takes a behavioral description of the complete system and generates another behavioral description of the same system in which each custom, semicustom or standard chip is described separately. Chip synthesis converts the behavioral description of each chip into a structural description with register-transfer (RT) components. We will discuss several alternatives for synthesis systems and the technical justification behind approaches taken in those alternatives. The work on design methodology is scarce and no high-level synthesis (HLS) systems are widely used in practice. In this chapter, we mainly discuss requirements for HLS systems and propose possible solutions, sometimes based on our own work but most often based on speculations on the nature of other work in industry and academia.