Design methodology for full custom CMOS microcomputers

Abstract

A highly structured design methodology is necessary to be successful in the design of VLSI integrated circuits with more than 100000 transistors on a chip. Such a methodology is described: it is based on the regularity of the circuit architecture with an associated chip floor plan and on a new layout technique named metal oriented layout. This methodology has been tested with the design of a 13500 MOS microcomputer. From the instruction set and through different levels of instruction interpretation, the architecture and associated chip floor plan are generated. The detailed logic design is made directly in symbolic layout with the chip floor plan in mind. The proposed design methodology can be best appreciated by the short development time and small chip area required for the designed 13500 MOS microcomputer.