Design Methodology and Jitter Analysis of a Delay Line for High-Accuracy On-Chip Jitter Measurements

Abstract

This work presents the design methodology and jitter analysis of a delay line for high-accuracy on-chip jitter measurements. Jitter generated in the delay lines degrades the accuracy of on-chip jitter measurements, and required to be minimized. In order to analyze and the jitter generation in the delay lines, SPICE simulation was performed with 65 nm CMOS technology. Simulation results show that jitter due to thermal noise can be reduced by enlarging the transistor sizes of both PMOS and NMOS. Based on the results, design methodology of a delay line is introduced for minimizing the jitter generation.