Design issues for low voltage, high speed folding and interpolating A/D converters

O Carnu,A Leuciuc

doi:10.1109/mwscas.2002.1187286

Design issues for low voltage, high speed folding and interpolating A/D converters

O Carnu, A Leuciuc

https://doi.org/10.1109/mwscas.2002.1187286

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Publication Date: Aug 4, 2002

Citations: 9

Affiliation: State University of New York

#High Speed Folding #A/D Converter + Show 7 more

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Abstract

In this paper are discussed design issues for a folding and interpolating A/D converter (ADC) in 0.35 /spl mu/m CMOS technology. A new averaging technique is used for reducing the DNL and INL errors. The goal is a speed of 100 MS/s and a resolution of 10 bits with a supply voltage of 2.5 V or less.

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