Design issues and an architecture for the monolithic implementation of a parallel digital signal processor

Abstract

Design issues in the implementation of a parallel digital signal processor for measurement systems are discussed. Constraints imposed by the application and VLSI technology are shown to lead to the design criteria of modularity, flexibility, programmability, and high speed. An architecture for the monolithic implementation of a parallel digital signal processor based upon these criteria is then presented. The use of asynchronous, self-timed function units each consisting of an instruction queue, data queues, and combinational logic is supported. Data and control interlocks are used for synchronization within the processor to facilitate both fine and coarse-grain parallelism. A programming example and simulation results are presented for a finite impulse response (FIR) filter. These results confirm the digital signal processor's efficiency. Using a conventional synchronous design, the simulation of a single prototype processor is presented. This design requires six clock cycles to compute a radix-2 fast Fourier transform (FFT) butterfly compared to 12 instruction cycles for a TI TMS320C30. Compared to a Motorola DSP 56001, the prototype processor permits a faster instruction cycle and less I/O overhead. It is estimated that a 1024-point FFT can be sped up 10 times using 10 processors.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>