Design, implementation, and performance evaluation of an earliest-deadline-first packet scheduling scheme in P4 hardware switches

Abstract

Real-time applications such as video conferencing, virtual reality (VR), high-speed train controls, nuclear plant controls, etc. impose stringent limitations on the maximum end-to-end latency that their packets can tolerate. In such applications, if a packet arrives at its destination node but misses its deadline, it will be useless. On a network, a packet often needs to pass multiple switches on its way from its source node to its destination node. In some of these switches, the packet may experience large queuing delays and the accumulation of these delays may cause the packet to miss its deadline at its destination node. In this work, we design and implement an earliest-deadline-first (EDF) packet scheduling scheme in P4 hardware switches to overcome this problem. We implement two versions of our scheme that use two queues and six queues respectively for real-time packets to study how the number of queues may affect the performance of our scheme. We evaluate the performance of our scheme under different levels of congestion conditions. Experimental results show that, compared with the baseline scheme that dispatches all real-time packets to the same high-priority queue, our scheme greatly reduces the deadline miss rate of real-time packets when the real-time traffic ratio in the network is between 40% and 80%.