Design, Implementation and Analysis of Different Models of CMOS Schmitt Trigger

Abstract

As the world is currently heading towards an era of prolonged battery life which has forced the chip designers to go for the scaling down of the supply voltage i.e. to operate in the sub threshold region for the reduced power supply consumption, thereby causing the performance deterioration of the circuit in terms of the noise immunity. So, comes the need of such a circuit which can be used as a provision for improving the noise immunity of the circuit, thereby resulting in the development of the Schmitt trigger. This paper presents the circuit design of low voltage high speed Schmitt trigger with the feature of adjustable hysteresis, which is implemented using the body biasing technique and a comparison of the results in terms of the propagation delay is presented with respect to the conventional Schmitt trigger circuit in 180nm CMOS technology using Cadence Virtuoso. Also, the effect of the body biasing voltage for controlling the width of the hysteresis-loop is shown thereby suggesting the appropriate voltage of the body terminal of CMOS transistors based upon the fact that greater the width of the hysteresis loop greater will be the immunity of the circuit.