Design for testability of an asynchronous adder

Abstract

Different designs of an asynchronous adder and their testability properties have been investigated in this paper. The single-rail implementation of an asynchronous adder is least complex in terms of number of gates, and is fast, but it demonstrates low stuck-at fault testability due to the logic redundancy in its control part. The logic testing of a single-rail asynchronous adder requires a special test mode to be implemented in order to remove its logic redundancy. As a consequence, stuck-at faults which have not been detected in normal operation mode can be identified in test mode. The dual-rail and hybrid implementations of the asynchronous adder are fully testable for stuck-at faults in normal operation mode but they require more area and exhibit lower performance. The dual-rail implementation of an asynchronous adder is faster than the hybrid adder but requires more silicon area. The dual-rail and hybrid adders can be used in asynchronous VLSI designs where performance and area overhead are not critical but testability in normal operation mode is important. The testable single-rail version of the adder can be used in asynchronous VLSI circuits which can be tested in both normal operation mode and test mode.