Abstract
The integration of copper (Cu) and low-k dielectrics has posed challenges for stress migration (SM) reliability. Besides process tuning, design for manufacturability (DFM) approach is proposed to suppress stress-induced void failures. In this paper, a three-dimensional (3D) finite element analysis (FEA) simulation model was used to identify the main mechanisms of several key processes and design approaches responsible for SM reliability improvement reported in the literature. On the basis of understanding the critical parameters and design/structural weak points affecting SM reliability, DFM is proposed to enhance the SM reliability of future nanoscale technologies employing porous ultra low-k dielectrics. The study illustrates the importance of process and design interactions to make porous ultra low-k Cu interconnects more resilient to SM degradation for future CMOS technologies.
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