Design for enhancing the performance of Advance Encryption Standard algorithm VHDL

Abstract

Now-a-day's network security has become an important issue. Security is most important part in data communication system. Fast progress of data exchange in electronic way, security of information is most important in data storage and also while transmission. That's why in this paper the designing of all circuit is made combinational design. Using of this combinational circuit there is zero delay at the output side. The Advance Encryption Standard (AES) is recently accepted symmetric cryptography for transfer of block of data. The data which is transmitted from sender to receiver in the network must be encrypted by using encryption algorithm. Next is by using decryption technique the receiver can view the original data. The AES sequence of four primitive functions that is Sub Bytes, Shift Row, Mix Column and Add Round Key. The AES cryptography algorithm is used to encrypt or decrypt the blocks of 128 bits. And also it is capable of using cipher keys of 128 bits (AES 128). Using this algorithm it will leads to an increase in the message encryption throughput. These methods will experimentally simulating with (VHDL) Verilog Hardware Description Language.