Design, fabrication, and performance of scaled analog ICs

Abstract

This paper concerns scaled MOS circuits for high-speed and high-density analog LSIs. The effect of scaling the devices employing three different scaling laws (constant electric field, constant voltage, and quasiconstant voltage laws) is examined using both the first-order approximation and two-dimensional device simulator. Versatile scaling relationships for analog circuits are then developed. They show that the bandwidth, transient response, and low-frequency gain are generally improved; however, the signal-to-noise ratio (S/N) is reduced by a scaling factor of k/SUP 0.5/ or k depending on which scaling law is used. To further investigate the scaling effects, scaled NMOS op amps are developed based mainly on the quasi-constant voltage law with k of approximately 2 and 3 compared to the conventional 8.5 /spl mu/m rule NMOS op amp. Improvements in slew rates and gain-bandwidth products are more than sixfold while keeping the low-frequency open-loop gain, power dissipation, and S/N almost unchanged.