Abstract
Topological insulator (TI) is recently discovered nano-device whose bulk acts as insulator but surface behaves as metal. As state information in a TI device is conducted by ordered spins, it draws tremendous interest for ultra-low power computing. This paper shows a state-space modeling and design exploration of TI device for non-volatile memory (NVM) design. The non-traditional electrical state in TI is extracted and modeled in a SPICE-like simulator. The model is the employed for hybrid CMOS-TI NVM design explorations for both memory cell and memory array. The experiment results show that TI based NVM exhibits a fast write and read latency as low as 20ns. In addition, compared to other emerging NVM technologies, it exhibits several orders of magnitude lower operation energy.
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