Design Considerations of an Amorphous Silicon Demultiplexer

Z Hafdi

doi:10.5755/j01.eee.19.8.5397

Abstract

This paper deals with the optimization of amorphous silicon gate driver circuits for active matrix array applications. It is based on static and dynamic models for hydrogenated amorphous silicon thin-film transistor operations. The models are extended to investigate amorphous silicon demultiplexer functionality. The proposed circuit is an improvement of an earlier published architecture. The circuit performance is discussed and demonstrated to be more reliable. It is shown that the response of the demultiplexer in terms of charging/discharging time is improved, the feed-through is reduced and the optimization of the circuit response is a reliable trade-off between stability and speed. This may contribute to overcome amorphous silicon technology shortcomings. DOI: http://dx.doi.org/10.5755/j01.eee.19.8.5397

Highlights

In amorphous silicon (a-Si) technology, we deal with lower device performance compared to single crystal silicon
Despite extensive study of amorphous silicon thin-film transistors’ (a-Si:H TFTs) electrical instability [3], careful design is still needed for reliable circuits
A variant of one of these gate drivers using an analytical model of a coplanar structure of amorphous silicon TFT is presented

Summary

INTRODUCTION

In amorphous silicon (a-Si) technology, we deal with lower device performance compared to single crystal silicon. Despite extensive study of amorphous silicon thin-film transistors’ (a-Si:H TFTs) electrical instability [3], careful design is still needed for reliable circuits. Some of these circuits are gate drivers for AMLCDs’ and AMOLEDs’ applications. Several architectures were proposed [4]–[7] and, despite their feasibility and applicability, they present advantages and shortcomings due to the limitations of amorphous silicon. Their characteristics depend on the techniques used for implementation [8].

CIRCUIT DESCRIPTION

DEMUX PERFORMANCE

Findings

CONCLUSIONS