Design considerations for surface-controlled negative-impedance transistors (NEGIT)

Abstract

A negative impedance transistor (NEGIT) is realized by placing a gate on the oxide over the emitter-base junction and attaching it to the collector. Careful study of two models describing the increase of base surface current with increasgate voltage shows that small geometry devices can be designed with the gate just covering the e-b junction and not extending significantly over the base surface. Based on this principle, I.C. devices have been designed and realized, with the gate covering less than 100% of the e-b junction to allow emitter contacting. Experimental results confirm the design principle. Devices with the gate extending respectively 4 and 9 µm over the base show almost identical characteristics in the voltage region corresponding to the maximum rate of collector current decrease. The smallest geometry devices fabricated occupied an area 5.5 mils × 5.25 mils. Dynamic common-emitter characteristics maybe displayed by pulsing the gate of an “uncommitted” gate device used in a Darlington configuration.