Abstract
This paper presents a methodology for selecting the architecture and optimizing the circuit design for the first block in a current-mode receiver chain, the low noise transconductance amplifier (LNTA). This methodology includes system-level considerations to select circuit design techniques for noise cancellation, linearity improvement and power reduction. The methodology is applied on an LNTA design in 28nm UTBB-FDSOI CMOS. The selected amplifier topology is designed to operate at 2.4GHz with a transconductance of 15mS. It achieves 2.67dB noise figure (NF), 1dB compression point (P1dB) of −7dBm, 9.5dBm input third order intercept point (IIP3) and consumes 1.5mA from a 1.2V supply.
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