Design Considerations for a 11.3 Gbit/s SiGe Bipolar Driver Array With a <inline-formula> <tex-math notation="LaTeX">$5\times \text {6 V}_{\mathrm {pp}}$ </tex-math> </inline-formula> Chip-to-Chip Bondwire Output to an MZM PIC

Abstract

This paper presents the design of a 5-channel driver array IC with a high total output current of $5\times \text {120 mA}$ and a $6~\mathrm {V}_{\mathrm {pp}}$ differential output voltage in SiGe bipolar technology. Special attention is given to design considerations for stable electrical and thermal operation and to the minimization of cross-coupling between the array channels. The related driver array is intended to realize a low-cost, small footprint $10\times \text {11.3 Gbit/s}$ dense wavelength division multiplexing transmitter assembly, consisting of a pair of two driver ICs with a chip-to-chip bondwire interface to a ten-channel Mach–Zehnder modulator (MZM) in a photonic integrated circuit (PIC). The driver IC contains all required components, including the far-end terminations of the MZMs as well as an energy-efficient concept for flexible MZM biasing. Current hogging in the transistors of the output stages is mitigated by a novel circuit concept that is introduced along with an electro-thermal model for dense multi-transistor arrangements, especially in driver output stages. The performance of the design is demonstrated by measurement results of the driver array IC in both standalone and integrated PIC assemblies.