Design Considerations for a 100 Gbit/s SiGe-BiCMOS Power Multiplexer With 2 $V_{{\mathrm{pp}}}$ Differential Voltage Swing

Abstract

This paper presents design considerations for an 8:1 multiplexer (MUX) circuit in a SiGe BiCMOS technology intended to be monolithically integrated together with a plasmonic Mach–Zehnder modulator on a single chip. It is shown why a power MUX (PMUX) architecture, where the final MUX selector stage directly drives the load, is beneficial to obtain high data rates and high output voltage swings at comparatively low power consumption. Therefore, the relation between the clock input amplitude and parasitic capacitances on the rise time of the PMUX is analyzed. Owing to the importance of the clock signal to the PMUX performance, design considerations for the clock distribution are presented. The design concept is proven by electrical measurements that demonstrate a record performance by clear output eye diagrams at 100 and 140 Gbit/s with 2.0 $V_{\text {pp}}$ and 1.2 $V_{\text {pp}}$ differential output voltage swing, respectively. The 2.6mm $\times $ 1.7mm MUX chip is implemented in IHP SG13G2 SiGe BiCMOS technology and consumes 7.15 W on a single −5.5-V supply voltage.