Design and VLSI implementation of mod-127 multiplier using cellular automaton-based data compression techniques

Abstract

A new technique for the design and VLSI implementation of a mod-127 multiplier based on two-dimensional cellular automata (CA) is presented in this paper using two-micrometre CMOS design rules. This technique uses the data compression capabilities of CA, which arise due to the availability of symmetrical global states, to reduce the silicon area required for these modulo arithmetic units by about 90%. The reduction in silicon area is achieved by using two identical triangular CA, each comprising 15 cells and an overflow bit, which are subjected to specific initial and boundary conditions. Encoding and decoding is performed on-chip and the complexity of the latter is significantly reduced by observing only a few critical cells that provide the signature for ascertaining the states of the CA. The silicon area occupied by the chip is 2.4 × 2.2 mm2 and it can operate with a clock frequency of 25 MHz with calculations requiring between 1 and 126 clock cycles to perform. VLSI complexity of the new approach is also compared with that of conventional ones. The paper has demonstrated the flexibility of the CA array architecture, in terms of modularity and parallelism, which is particularly well suited to implementation using VLSI.