Design and verification of DFE re-decision algorithm for PAM6 high-speed transceiver based on FPGA

Abstract

In this paper, a decision feedback equalizer (DFE) re-decision algorithm for a 6-level pulse-amplitude-modulation (PAM6) high-speed transceiver is proposed. PAM6 is a two-dimensional (2D) modulation. The four outer points are not used in the 2D constellation diagram to reduce the output power. Although the four outer points will not be modulated, they may be encountered during demodulation. This paper considers the above situation and theoretically analyzes the DFE module under the additive white Gaussian noise (AWGN) channel. Compared with the traditional pipelined DFE structure, the proposed algorithm can help solve the four outer points in PAM6. A serializer/deserializer (SerDes) simulation system is built based on a field programmable gate array (FPGA), and the performance of the proposed algorithm is carried out on the simulation system. According to this proposed algorithm, the symbol error rate (SER) of the PAM6 SerDes system can be reduced, and the system performance can be improved. When the DFE tap coefficient is 0.50 and the signal-to-noise ratio (SNR) is 22.0 dB, the proposed algorithm can additionally correct 8.18 % of erroneous symbols. When the DFE tap coefficient is 1.00 and the SNR is 22.0 dB, the proposed algorithm can additionally correct 17.30 % of erroneous symbols.