Design and validation of a novel reconfigurable and defect tolerant JTAG scan chain

Abstract

In this paper, a novel technique to get a defect tolerant JTAG compliant scan chain in very large area integrated circuits (VLAIC) is presented. It was ruled that wafer-scale VLAICs require structural regularity and defect-tolerance to be cost effective. Using only one scan chain, as typically used in PCBs, would make the whole VLAIC unusable if a single defect is present in the chain. The proposed technique regularly distributes JTAG Test Access Port (TAP) controllers with test data ports linked to two or more neighbor test data ports. One TAP controller is wired as the entry point and another as the exit point of the scan chain that must be configured according to defect locations. An externally controlled wormhole like routing algorithm can be used for functional link discovery. This paper also proposes a mechanism to make defect tolerant access to test data registers, controlled from neighbor TAP controllers. Our technique has been successfully implemented and validated in a wafer-scale like integrated circuit used in a platform for electronic system prototyping. The logic area of this defect-tolerant configurable JTAG scan chain technique occupies 5% of the test logic and 0.3 % of the cell logic when links to four nearest neighbors are included.