Abstract

A low noise amplifier (LNA) with an on-chip dual notch filters for the rejection of blockers at the 3rd and 5th harmonic frequencies is presented in this work. A resistive feedback current-reuse (RFCR) architecture is utilized to provide broadband input impedance matching, low noise, and high linearity simultaneously. The proposed LNA has been designed using 40nm CMOS technology and verified from the post-layout simulations. With Band 8 (880MHz - 915MHz) operating frequency range, the proposed LNA attained a maximum power gain (S 21 ) of 23 dB, minimum noise figure (NF) of 3.7 dB. The 3rd and 5th harmonic rejections are 36.5 dBc and 45.5 dBc when injected with 0.9 GHz input frequency.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.