Design and Tool Flow of IBM's TrueNorth

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Developing scalable real-time systems that can simultaneously process massive amounts of noisy multi-sensory data, while being energy efficient, is a dominant challenge in the new era of cognitive computing. Low-power, flexible neurosynaptic architectures offer tremendous promise in this area. To this end, we developed TrueNorth, a 65mW brain-inspired processor that implements a non-von Neumann, parallel, distributed, event-driven, modular, scalable, defect-tolerant architecture. With 4096 neurosynaptic cores, the TrueNorth chip contains 1 million digital neurons and 256 million synapses tightly interconnected by an event-driven routing infrastructure. The fully digital 5.4 billion transistor implementation leverages existing CMOS scaling trends, while ensuring one-to-one correspondence between hardware and software.Given that the TrueNorth architecture breaks path with prevailing architectures, conventional tool flows could not be used for the design. Therefore, we developed a novel design methodology that includes mixed asynchronous-synchronous circuits, interfaces, and a complete tool flow for building an event-driven, low-power neurosynaptic chip. Further, we have adapted existing VLSI CAD placement tools for mapping logical neural networks to the physical core locations on the TrueNorth chip to reduce the network's communication energy.The TrueNorth chip's low power consumption is ideal for use not only in large-scale computationally intensive applications, but also for embedded battery-powered mobile applications. The chip is fully configurable in terms of connectivity and neural parameters to allow custom configurations for a wide range of cognitive and sensory perception applications. We have successfully demonstrated the use of TrueNorth chips in multiple applications, including visual object recognition, with higher performance and orders of magnitude lower power than the same algorithms run on von Neumann architectures.