Design and Testing of a Prototype ASIC for the MTPC Readout at CSNS Back-n White Neutron Source

Abstract

In this paper, a prototype Application Specific Integrated Circuit (ASIC) for the Multi-purpose Time Projection Chambers (MTPC) at Back-n White Neutron Source is presented. The ASIC integrates 16 readout channels and is fabricated in a 0.18 μm CMOS process. Each channel consists of a Charge Sensitive Amplifier (CSA), a Pole-Zero Cancellation (PZC), two bridged-T shapers, a baseline holder, and a fully differential output buffer. It provides selectable charge ranges of 2 pC and 10 pC, programmable peaking times from 110 ns to 1 μs, and an adjustable output common-mode voltage from 0.7 V to 1.25 V. The ASIC has already been tested and all the results meet the requirements. In the case of 100 pF input capacitance, 2 pC charge range, and 1 μs peaking time, it features a maximum Integral Non-Linearity (INL) of 0.48% and an Equivalent Noise Charge (ENC) of 0.749 fC, which makes the Signal-to-Noise Ratio (SNR) at full-scale input over 2600. In particular, a crosstalk rejection ratio of 63 dB is obtained in this prototype ASIC by using the baseline holder circuit in each channel to generate references for single-ended to differential conversion, isolating noise and crosstalk from the reference path.