Design and Study of performance of nano-scale FINFETs with reduced switching energy using spacer optimization

Abstract

VLSI trends are in focus to reducing gate sizes for miniaturization of circuits to be on par with the Moore's law which states that the number of transistors in a unit area doubles every 18 months. To make this possible, transistor gate sizes must be reduced. More shrinkage of gate size leads to short channel and leakage effects which are undesirable making CMOS impossible to use beyond 22nm. To replace CMOS in circuits, another type of Field Effect Transistor called FINFETs are deployed. They are multigate devices and so, they control leakage and other short channel effects. They are more efficient in performance than CMOS, but because of multigate, the parasitic resistance and capacitance is more than that of CMOS. This limits its analog performance. This paper focuses on reduction of parasitic capacitance of 20nm FINFET by optimizing the gate spacer material used. The simulations are done on Synopsys TCAD tools and finally the circuits using the optimized FETs are simulated using HSPICE to measure parameters like delay, power, etc.