Design and simulation of nano scale mosfet for next generation VLSI circuits

Abstract

Nowadays, the development of VLSI technology is mainly directed towards the miniaturization of semiconductor devices which in turn is heavily dependent on the advancement in the CMOS technology. The minimum dimension of a single device for present day technology is below sub-100 nm in channel length. As CMOS technology dimensions are being aggressively scaled down to the fundamental limits (such as reduction in carrier mobility due to impurity, increasing gate tunneling effect as the gate oxide thickness decreases, increasing p-n junction leakage current as the junction become more and more shallow, etc.) imposed by the material characteristics, secondary effects begin to influence the device performance significantly and more accurate device models as also innovative MOS device structures are required to be necessarily developed. These requirements have led to development of alternative technology. Silicon-On-Insulator(SOI) technology is one such alternative which can offer the performance as may be expected from next generation Si technology. In this work, symmetric Dual-Material Double Gate Fully-Depleted SOI MOSFET has been analyzed. The analytical model for the MOSFET's electrical parameters (such as potential distribution, electric field distribution, electron velocity distribution, sub-threshold swing, threshold voltage, device capacitance, drain-current, trans-conductance, drain-resistance, cut-off Frequency and transit time) has been developed and compared with the results for the device parameters obtained by numerical analysis using ATLAS. It has been observed that this structure provides for significantly improved efficiency and high frequency behavior of the device. Also the accurate device models are required for designing VLSI circuits, the impurity distribution in the body region has been.