Design and simulation of hybrid SET-MOS pass transistor logic based universal logic gates

Abstract

In order to improve density of integration in VLSI chips and to ensure ultra low power dissipation Co-design of MOS transistor along with Single electron transistor is considered as one of the best option to work with. In the present work we have designed universal logic gates using hybrid SET-MOS based pass transistor logic. The logic gates are consists of one Single electron transistor and one NMOS transistor, both are working as pass transistors. In this paper we have designed NAND and NOR logic gates by providing inputs in their original and complemented form to the different nodes of the pass transistors depending upon the realization of that particular logic gate.