Design and Simulation of Controller Area Network Module Using Verilog HDL

Abstract

Abstract: Controller Area Network or CAN protocol is a method of communication between various electronic devices. It has significant use in the industry of automobiles. It defines a standard for efficient and reliable communication between sensor, actuator, controller, and other nodes in real-time applications. This provides a mechanism which is incorporated in the hardware and the software by which different electronic modules can communicate with each other using a common cable. CAN protocol is a message-based protocol, not an address-based protocol. All nodes in the system receive every message transmitted on the bus (and will acknowledge if the message was properly received). It is up to each node in the system to decide whether the message received should be immediately discarded or kept to be processed. The main aim is to design, development, and implementation of a CAN module using Verilog HDL. The intent is to show that the designed CAN module can replace a standalone CAN controller which occupies extra space in the system. Also implementing the CAN with the help of custom RAM is aimed at removing the need for FPGA specific RAM. The proposed design of CAN module is an integration of lower-level modules. The desired Verilog implementation of CAN module can help in simulating different systems at the design level instead of using physical ICs. The design includes a simple scheme that aims in reduction of circuit complexity and chances of hardware failure without requiring any extra logic circuitry.