Abstract
This paper proposes a system-in-package combination navigation chip. We used wire bonding, chip stacking, surface mount, and other processes to integrate satellite navigation chips, inertial navigation chips, microprocessor chips, and separation devices. Finally, we realized the hardware requirements for combined navigation in a 20 mm × 20 mm chip. Further, we performed a multi-physics simulation analysis of the package design. For antenna signals, the insertion loss was greater than -1 dB@1 GHz and the return loss was less than -10 dB@1 GHz. The amplitude of these noises of the signal between the MCU and the IMU was approximately 20%, and the maximum value of the coupling coefficient between signal lines on the top surface was 13.4174%. The ninth mode of the power plane yielded a maximum voltage of 55 mV, and all power delivery networks had a DC voltage drop of less than 2%. The highest temperature in the microsystem was approximately 42 °C. These results show that our design performed well in terms of signal, power, and thermal performance.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.