Design and Simulated Annealing Optimization of a Static Comparator for Low-Power High-Speed CMOS VLSI

Abstract

In this work, we present a new architecture for designing static low-power high-speed comparators based on tristate buffers. The delay of this structure is a logarithmic function of the fan-in. With a minor modification, the circuit can be optimized for high speed or low power operation. The performance of the circuit has also been optimized using simulated annealing method. To assess the efficiency of the comparators, they have been simulated in a 100nm CMOS technology. The results for VDD = 1V show a maximum delay of 302ps (570ps) and a power consumption of 614μw (150μw) for a 64 bit high-speed (low-power) comparator at 2GHz. Compared to a conventional tree comparator, the high-speed (low-power) circuits show a 9 (10) times better energy delay product (EDP).