Design and realization of 1.3 Gb/s off-chip transmission circuitry using 0.35 μm CMOS technology

Abstract

Low-voltage-differential-signaling (LVDS) is one of the very popular technologies which simultaneously addresses low dynamic power consumption and high data rate transmission in modern high speed circuit applications. In this paper, system level integration design approach is applied to design LVDS transmitter featuring high off-chip data rate. Full wave electromagnetic simulation technique was adopted to accurately characterize possible couplings and parasitic effects induced from the off-chip components which then acted as the termination of the output circuitry. Common mode feedback was included to perform fine tuning on the offset leading to much higher overall precision. Meanwhile, generation of the controlled current and voltage across termination was guaranteed through the introduction of a constant transconductance bias network. The design was implemented using TSMC 3.3 V 0.35 μm CMOS technology with overall chip size of 0.923 mm2. At a DC power consumption level of 29.4 mW, the LVDS transmitter exhibited an off-chip data rate of 1.3 Gb/s validated through measurements.