Design and Prototyping Flow of Flexible and Efficient NISC-Based Architectures for MIMO Turbo Equalization and Demapping

Mostafa Rizk,Youssef Atat,Michel Jézéquel,Yasser Mohanna,Amer Baghdadi

doi:10.3390/electronics5030050

Abstract

In the domain of digital wireless communication, flexible design implementations are increasingly explored for different applications in order to cope with diverse system configurations imposed by the emerging wireless communication standards. In fact, shrinking the design time to meet market pressure, on the one hand, and adding the emerging flexibility requirement and, hence, increasing system complexity, on the other hand, require a productive design approach that also ensures final design quality. The no instruction set computer (NISC) approach fulfills these design requirements by eliminating the instruction set overhead. The approach offers static scheduling of the datapath, automated register transfer language (RTL)synthesis and allows the designer to have direct control of hardware resources. This paper presents a complete NISC-based design and prototype flow, from architecture specification till FPGA implementation. The proposed design and prototype flow is illustrated through two case studies of flexible implementations, which are dedicated to low-complexity MIMO turbo-equalizer and a universal turbo-demapper. Moreover, the flexibility of the proposed prototypes allows supporting all communication modes defined in the emerging wireless communication standards, such LTE, LTE-Advanced, WiMAX, WiFi and DVB-RCS. For each prototype, its functionality is evaluated, and the resultant performance is verified for all system configurations.

Highlights

To follow the evolution in wireless communication applications, the rapid design and implementation of embedded systems are vital factors
The hardware-measured bit error rate (BER) shows acceptable performance degradation when compared to floating-point C simulations
The obtained synthesis results show that a low number of slices is utilized to implement the no instruction set computer (NISC)-based equalizer and demapper architectures

Summary

Introduction

To follow the evolution in wireless communication applications, the rapid design and implementation of embedded systems are vital factors. The utility of application-specific processors is of an increasing extent, since they provide a good solution in designing efficient hardware architectures that can satisfy the tight constraints on the implementation area and power consumption and nowadays fulfill the requirements in terms of high throughput. Electronics 2016, 5, 50 and low error-rate performance These facts motivate exploiting design and prototype flows that are capable of providing high design quality, as well as increased design productivity. Wireless digital communication standards are developing continuously. This work concerns the design and the implementation of flexible and high performance application-specific processors dedicated to the equalizer and the demapper modules of the turbo-receiver. Each block generates soft information depending on channel information and on received a priori soft information generated by other blocks in the previous iteration

Objectives

Results

Conclusion