Design and performance of a product code turbo encoding-decoding prototype

Abstract

This paper presents the latest results on a block turbo decoder design. We propose a block turbo decoder circuit for the error protection of small data blocks such asAtm cells on anAwgn (additive white Gaussian noise) channel with a code rate close to 0.5. A prototype was developed atEnst Bretagne. It allowsBer (bit error rate) measurements down to 10−9 and uses programmable gate arrays (Fpga Xilinx circuits). The elementary extendedBch code and the data block size can be modified to fit specifications of different applications.