Abstract
The design of distributed amplifiers (DAs) is one of the challenging aspects in emerging ultra high bit rate optical communication systems. This is especially important when implementation in submicron silicon complementary metal oxide semiconductor (CMOS) process is considered. This work presents a novel design scheme for DAs suitable for frontend amplification in 40 and 100 Gb/s optical receivers. The goal is to achieve high flat gain and low noise figure (NF) over the ultra wideband operating bandwidth (BW). The design scheme combines shifted second tire (SST) matrix configuration with cascode amplification cell configuration and uses m-derived technique. Performance investigation of the proposed DA architecture is carried out and the results are compared with that of other DA architectures reported in the literature. The investigation covers the gain and NF spectra when the DAs are implemented in 180, 130, 90, 65 and 45 CMOS standards.The simulation results reveal that the proposed DA architecture offers the highest gain with highest degree of flatness and low NF when compared with other DA configurations. Gain-BW products of 42772 and 21137 GHz are achieved when the amplifier is designed for 40 and 100 Gb/s operation, respectively, using 45 nm CMOS standard. Thesimulation is performed using AWR Microwave Office (version 10).
Highlights
Everybody wants to benefit from the evaluation in the field of communication especially through internet
Fiber optic communication is a solution because high data rates can be transmitted through this high capacity cable with high performance [3]
The results show that when the cutoff frequency increases, the gain decreases for all distributed amplifiers (DAs)
Summary
Everybody wants to benefit from the evaluation in the field of communication especially through internet. BW requirements will increase by more than 100 times and applications such as virtual reality require data rate that are 10,000 times higher than currently available. To transport such data rate, a media with low loss and high BW is required [1, 2]. Optical fibers are very common these days to transport very high rate digital data. Fiber optic devices and systems are employed to realize very high data rates. Fiber optic communication is a solution because high data rates can be transmitted through this high capacity cable with high performance [3]. Design DA for 40 Gb/s (and above) optical receivers needs careful consideration related to the gain, frequency spectrum and NF.This paper addresses the design issues and performance investigation of CMOS DA for the front-end amplification stage in 40 and 100 Gb/s optical receivers
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