Design and performance evaluation of the ATM multicast shuffleout switch

Abstract

This paper describes a proposal of a multicast ATM switch whose interconnection network is the same as in the Shuffleout switch architecture, that is a multistage arrangement of switching elements in which the self-routing is accomplished by shortest-path and deflection routing. Packet replication is accomplished by means of a functionality added to each switching element that is therefore able not only to replicate the multicast packets as they go through the network but also to route the single copies to each addressed outlet. By suitably engineering the number of stages, the network is able to generate the total number of requested copies per slot within the target packet loss probability. An enhanced version is also discussed that is capable of limiting the packet replications per slot, so as to obtain the desired traffic performance with less network stages.