Abstract
paper presents a low power low voltage CMOS frequency divider using power gating technique, that's why it reduces the overall power consumption of circuit and increases the efficiency of circuit. This paper demonstrate various parameters and shows reduced leakage power (0.45*10 -12 ), Delay (6.26 psec) and noise margin (11.53 dB) of the circuit to analyze its performance in 45nm technology with power gating technology. The simulation results were done with cadence tool virtuoso environment at room temperature 27oC with various supply voltage ranges (0.7 to 1.2 V). Keywordsdivider, power gating technique, leakage power, Delay, Noise margin.
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