Design and performance analysis of one 32-bit dual issue RISC processor for embedded application

Abstract

One 32-bit RISC processor for embedded application is presented. With respect to the limitation of power and area in the embedded system, the RISC processor is deliberately designed. Dual-issue technology is adopted to improve the performance; the complex logic of the dynamic scheduling algorithm is allocated into different pipeline stage to improve the frequency. Lower power design method is used to decrease the whole power. The processor is implemented by SMIC 0.18 um CMOS technology. It contains almost 5 million transistors; the core frequency is 266 MHz and the power is about 1.3 w under it. The embedded VxWorks OS can run on it stably. The performance analysis of the RISC processor is also provided. According to the embedded benchmark program, the average IPC of the RISC processor is nearly 1.5.