Abstract
2.5 dimensional stacked integrated circuits (2.5D-SICs) with through-silicon vias (TSVs), as next generation silicon technologies, are promising to go beyond Moore’s law for compact, high-performance, energy-efficient microsystems. 2.5D-SICs with closely placed heterogeneous dies are considered a first step towards full 3D integration. In this paper, a novel micro-channel dielectric coolant manifold for 2.5D-SICs with multiple high-power dies, has been investigated. Five active dies are modeled with power maps of one 50 W, $25~ {\text {mm}} \times 25~{\mathrm {mm}}$ field programmable gate array (FPGA), and four high heat flux transceivers (30 W/each, $6~ {\text {mm}}\times 6~$ mm/each). In order to provide thermal management to this heterogeneous chip system, micro-fin-bridges and micro-pins have been implemented in the manifold. In addition, all dies have been immersed in the micro-channel with dielectric coolant to isolate the thermal interaction between dies. Effects of chips’ placement, dimensions of micro-fin-bridges and micro-pins, and dielectric coolant supply and removal locations within the manifold on pressure drop and heat transfer have been parametrically studied by full-scale computational fluid mechanics/heat transfer simulations.
Published Version
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