Design and Optimization of Synchronous Counter Using Majority Gate-Based JK Flip-Flop

Abstract

Complementary metal oxide semiconductor is an innovation that has changed the domain of hardware. CMOS scaling has achieved maximum limit, indicating adverse impacts not just from physical and mechanical perspective yet additionally from material and practical point of view. This drift move the analysts to search for new encouraging options in contrast to CMOS technology which indicates better execution, thickness and power utilization. To replace the CMOS technology different new technologies are developed in order to solve the different problems faced by CMOS. In this paper, new rising nanotechnology, quantum dot cellular automata is considered. Quantum dot cellular automata contributes in overcoming the difficulties faced by the CMOS technology now a days such as heat dissipation and scaling problems and hence improves the computation in different applications. For that reason, this paper propose the compatible architecture based on majority gate structures. This paper aims to present 2-bit and 3-bit synchronous counter as an application of a well-optimized JK flip-flop which is optimized on account of QCA. The proposed synchronous counter structure can be further extended to 4-bit and more. The advantage of the propound structure in comparison to previous circuits in terms of energy dissipation have been shown derived. QCADesigner E tool is used for the evaluation of the operational exactness of the designed structure.