Design and optimization of dual modulus prescaler using the extended true-single-phase-clock

Abstract

A low-power divide-by-4/5 unit of a prescaler is proposed. The power consumption and operating frequency of the extended true-single-phase-clock (E-TSPC)-based frequency divider is investigated. The short-circuit power and the switching power in the E-TSPC-based divider are analyzed. Compared with the existing design, a 20% reduction of power consumption is achieved. A divide-by-16/17 dual-modulus prescaler implemented with this divide-by-4/5 unit using a 0.18-um CMOS process is capable of operating up to 4.1 GHz with a low-power comsumpti-on. The prescaler is implemented in low-power high-resolution frequency dividers for wireless short distance application.