Design and optimization of an ultra-wide frequency range CMOS divide-by-two circuit

Abstract

A novel toggled flip-flop (TFF) divide-by-two circuit (DTC) and its optimization method based on a large-signal analysis approach are proposed. By reducing the output RC constant in tracking mode and making it large in latching mode, compressing the internal signal swing as well as compensating the current leaked in the latching mode, the operating frequency range is greatly expanded. Implemented in a SMIC 0.13 μm RF CMOS process with a 1.2 V power supply, it can work under an ultra-wide frequency band ranging from 320 MHz to 29.6 GHz. Experimental results show that two phase-locked loops (PLLs) with the proposed DTC can achieve in-band phase noise of −94 dBc/Hz @ 10 kHz under 4224 MHz operating frequency and −84 dBc/Hz @ 10 kHz under 10 GHz operating frequency, respectively. The power consumption of the proposed DTC is reduced by almost 50% compared with the conventional counterparts.