Abstract
The turbo decoder is the most challenging component in a digital HSDPA receiver in terms of computation requirement and power consumption, where large block size and recursive algorithm prevent pipelining or parallelism to be effectively deployed. This paper addresses the complexity and power consumption issues at algorithmic, arithmetic and gate levels of ASIC design, in order to bring power consumption and die area of turbo decoders to a level commensurate with wireless application. Realized in 0.13 nmum CMOS technology, the turbo decoder ASIC measures 1.2nmm2 excluding pads, and can achieve 10.8 Mb/s throughput while consuming only 32 mW.
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