Design and Optimization of an Area-efficient SOT-MRAM

Abstract

Spin orbit torque magnetic random access memory (SOT-MRAM) has attracted numerous research interests since it promises to overcome the write speed and energy bottlenecks of the conventional STT-MRAM. However, the cell density of SOT-MRAM is constrained due to more access transistors. In this work, we present a NAND-Like architecture for SOT-MRAM with a single transistor and several diodes, as well as a novel adaptive array design based on the proposed cell structure. Compared with the standard SOTMRAM, the proposed SOT-MRAM achieves significant improvement in the cell density by sharing transistors, meanwhile attains a comparable write speed. The overhead of write energy can be compensated by a well-designed write policy.