Design and Optimization of 650V/1200V Silicon Carbide MOSFET with Hybrid Junction Termination Extension (Hybrid-JTE)

Abstract

Silicon carbide (SiC) power devices have gradually replaced silicon devices in the field of medium and high voltage because of the wide band gap, high breakdown electric field and high thermal conductivity. Commercial SiC power MOSFET devices mainly include two voltage levels of 650V and 1200V. The terminal structure is mainly based on the field limiting ring (FLR) structure, which has good process feasibility but nonideal terminal efficiency. The junction termination extension (JTE) structure can achieve high termination efficiency, but its ion implantation process window is small and the process complexity is high. This paper uses the hybrid junction termination extension (Hybrid-JTE), which has higher terminal efficiency and good process window, to design 650V and 1200V SiC planar MOSFET. The structure parameters of cell and Hybrid-JTE terminal are designed and optimized by using TCAD simulation. Compared with the FLR, the SiC planar MOSFET with Hybrid-JTE has higher breakdown voltage and higher terminal efficiency. The tolerance of the RA-JTE structure parameters in the Hybrid-JTE to implant dose fluctuations was investigated by simulation, which shows that the addition of RA-JTE structure optimizes the process window of ion implantation.